Field of the Invention
The present invention relates generally to the field of integrated circuits, and, more particularly, to a clock and data recovery circuit.
Description of the Related Art
A clock and data recovery (CDR) circuit is commonly used in a high speed data communication system. Generally, the high speed data communication system receives a data signal without an accompanying clock signal. An absence of the accompanying clock signal may result in undersampling or oversampling of the data signal. Thus, a CDR circuit is used in the high speed data communication system to generate a clock signal at a frequency that is equal to the frequency of the data signal. Further, the clock signal samples the data signal at the frequency of the clock signal. The CDR circuit may be implemented with either an open-loop or closed loop architecture. The closed loop CDR circuit is easier to implement and is referred to as a phase-locking CDR circuit.
Typically, a conventional phase-locking CDR circuit (hereinafter referred to as “CDR circuit”) with a negative feedback control loop, includes a phase detector, an oscillator circuit, and a data sampler. The phase detector determines a phase difference between a phase of the clock signal and a phase of the data signal (also referred to as ‘phase lock mode’), and generates a frequency control signal based on the phase difference. The oscillator circuit receives the frequency control signal and generates the clock signal. The frequency control signal controls the frequency of the clock signal. Further, the data sampler receives and samples the data signal based on the clock signal.
At high speeds of data transmission, the phase detector of the conventional CDR circuit introduces ripple in the frequency control signal which in turn introduces jitter in the clock signal. Further, various delays such as clock-to-output delays and propagation delays in the phase detector introduce latency in the clock signal. To ensure that the phase detector provides a proportional feedback control in the CDR circuit, it is essential that the clock signal has low latency. The timing paths of the phase detector are represented by a unit interval (UI). The UI is a predetermined time interval which is equal to a bit time interval of a data signal. A full-rate phase detector operates on a clock signal that has a time period UI. A half-rate phase detector operates on a half-rate clock signal that has a time period 2UI.
A known implementation of the phase detector is a full-rate bang-bang (Alexander) phase detector (BBPD) that includes first through fourth flip-flops and first and second XOR logic gates. The first flip-flop receives the data signal and the clock signal, samples the data signal at a rising edge of the clock signal, and generates a first sample signal. The second flip-flop receives the data signal and an inverted clock signal (i.e., the clock signal that has a phase difference of 180 degrees with reference to the clock signal), samples the data signal at a falling edge of the clock signal, and generates a second sample signal.
The third flip-flop receives the first sample signal and the clock signal, samples the first sample signal at the rising edge of the clock signal after a time period of UI (i.e., resamples the data signal), and generates a third sample signal. The fourth flip-flop receives the second sample signal and the clock signal, samples the second sample signal at the rising edge of the clock signal after a time period of 0.5UI (i.e., resamples the data signal), and generates a fourth sample signal. The fourth sample signal is delayed by a time period of 0.5UI with reference to the second sample signal.
The first XOR logic gate receives the first and fourth sample signals and generates a first sampling signal. The second XOR logic gate receives the third and fourth sample signals and generates a second sampling signal. The first and second sampling signals provide early-late information of the clock signal with reference to the data signal. If the first and second sampling signals are at the logic low state, there is no transition of the data signal with reference to the clock signal. If the first and second sampling signals are at logic high and low states, respectively, the clock signal is late with respect to the data signal. Further, if the first and second sampling signals are at logic low and high states, respectively, the clock signal is early with respect to the data signal.
The first through fourth flip-flops are D flip-flops. The fourth flip-flop samples the second sample signal after the generation of the second sample signal (after 0.5UI time period). The clock-to-output delay of a D flip-flop may be greater than 0.5UI. Hence, the fourth flip-flop may fail to sample the second sample signal received from the second flip-flop exactly after 0.5UI time period. Thus, the full-rate BBPD may not generate the first and second sampling signals accurately, and consequently, fail to detect the correct early-late information. Further, as the time period of the clock signal is one UI, the first and second XOR logic gates have less time to generate the first and second sampling signals. Thus, faster processing first and second XOR logic gates are required to obtain the correct early-late information. Moreover, in order to generate accurate first and second sampling signals, it is essential that the first through fourth sample signals are stable for one UI.
A known solution to overcome the aforementioned problems is the use of a half-rate BBPD along with a quadrature clock signal. The half-rate BBPD includes first through third flip-flops, and first and second XOR logic gates. The first flip-flop receives the data signal and the clock signal, samples the data signal at a rising edge of the clock signal, and generates a first sample signal. The second flip-flop receives the data signal and a quadrature clock signal (i.e., the clock signal that has a phase difference of 90 degrees with reference to the clock signal), samples the data signal at a rising edge of the quadrature clock signal, and generates a second sample signal. The third flip-flop receives the data signal and the inverted clock signal, samples the data signal at the falling edge of the clock signal, and generates the third sample signal.
The first XOR logic gate receives the first and second sample signals and generates a first sampling signal. The second XOR logic gate receives the second and third sample signals and generates a second sampling signal. The first and second sampling signals provide the early-late information of the clock signal with reference to the data signal. If the first and second sampling signals are at the logic low state, there is no transition of the data signal with reference to the clock signal. If the first and second sampling signals are at logic high and low states, respectively, the clock signal is late with respect to the data signal. Further, if the first and second signals are at logic low and high states, respectively, the clock signal is early with respect to the data signal.
The first through third flip-flops are D flip-flops. As the clock signal is a half-rate clock signal, the time period of the clock signal is 2UI. The clock-to-output delay is not greater than UI and is thus, compensated for by the half-rate BBPD. Further, the first and second sample signals are not aligned (i.e., the first and second sample signals have a phase difference of 90 degrees between them). Similarly, the second and third sample signals are not aligned. Due to the misalignment of the first through third sample signals, glitches may occur in the first and second sampling signals. The glitches may result in incorrect early-late information. Moreover, the data signal may transition from one logic state to the other logic state during the setup and hold times (also referred to as the “uncertainty window”) of the first through third flip-flops. Hence, the first through third sample signals may be in a meta-stable state, causing the first and second sampling signals to be in a meta-stable state, which is undesirable. Thus, the half-rate BBPD may not generate the first and second sampling signals accurately, and consequently, fail to detect the correct early-late information.
It would be advantageous to have a BBPD that has low latency, accurately detects the early-late information, and overcomes the aforementioned drawbacks.